The present invention relates to flip-flops, and more particularly to a fast latching flip-flop for higher frequency clocking and faster data latching with a shortened metastable region.
In digital systems where input signals come from different sources with no common time reference, signals may occur which are not logically defined. The interactions between these systems are asynchronous. An example is a test instrument, such as a logic analyzer, which has an internal clock to provide internal synchronization but which samples signals from devices under test having an unrelated clock. This means that data samples taken by the test instrument are random in time with respect to the internal clock, and an input signal may change during a sample clock edge of the internal clock. To prevent system failure a synchronizer, such as a flip-flop, is used at the input to the test instrument to provide reliable communication between asynchronous systems.
In an ECL master-slave D-type flip-flop there is a transparent data input amplifier followed by a latch. In operation the data is input to the input amplifier and transferred to the latch at the leading edge of a clock pulse. The clock pulse turns off the input amplifier and turns on the latch. Due to the parasitic capacitances of the components there is a period of time during which the input amplifier is off before the latch is on. During this period new data at the input will not be transferred to the latch, or will cause the latch to make an erroneous or random decision. This period commonly is referred to as the metastable region. A typical flip-flop of this type has a metastable region on the order of 600 picoseconds. However, where an acquisition accuracy for the data of 0.5 nanoseconds is desired, a metastable region of much shorter duration is desired.